This invention relates generally to data display and control systems and more particularly to graphics controllers which are programmable to enable smooth panning capabilities beyond the video display memory limit.
Various systems have been realized to display computer graphics information so as to make manipulation and use of such information both easy and flexible. The conventional graphic system includes a CRT which is controlled by a display control system which may comprise a CRT controller, a visual attribute generator, as well as memories including display and screen memories and serial digital memories or random access digital memories. With such systems, by displaying data on the screen of a raster-scan cathode ray tube the resulting display pictures can be of very high complexity and may include other display options.
For many application it is desired that the user be able to sort through textual or graphic information in a video display system both quickly and easily. The scroll and pan functions which have been developed to enable the user to more rapidly view data have been improved so as to smoothly move the data over the screen. In one improved system as shown in U.S. Pat. No. 4,714,919, there is disclosed a video display system and method for continuous smooth scrolling in which the video image is displaced upwardly one scan line by means of a display vertical position control and new data is accessed by corresponding start address updating in video memory. In this system, the operation of the display vertical position control must coincide with the vertical sync pulse interval and is restricted by the video display memory limit.
The panning capability is also very important in many applications such as a display of wave form data such as pressure, physical potentials, temperature, electrical drift and the like. In one system as found in U.S. Pat. No. 4,442,495, there is shown a video display system and panning control system in which graphic image data is accessed from a video memory which has a larger dimension than that which may be viewed on the screen of a CRT. In the excess memory there is stored image data which forms a continuation of the image displayed such that panning into the excess memory is enabled. There is also provided a rewrite area in video memory for inputting new information which may subsequently be viewed on the screen according to timing circuits which limit the rate at which panning can occur. Although smooth panning is enabled by this system, the rate of panning is limited and the screen must be refreshed when the video memory limit is reached.
In other systems, the screen memory can be moved about in the video memory by use of graphics controllers such as the Enhanced Graphics Adapter and Video Graphics Array as developed by IBM and included in graphic display systems of personal computers such as the IBM PC/2. The memory configuration of these graphic controllers may include 256K of display memory configured as four 64K planes. In this system, each scan line on the screen will have a default length of 80 bytes of video memory.
The graphic controller hardware supports logical line lengths allowing one to configure a number of display memory bytes which will equal one screen width. Thus, the logical screen width may be set to be greater than the actual screen width whereby panning can be achieved within the limits of the video memory.
A horizontal pixel panning register forming part of the visual attribute generator in the graphic controller is a read/write register pointed to by the value in the attribute address register. The register allows the video image to be panned up to 8 pixel positions in certain video modes and continuous panning is achieved by incrementing the panning register in accordance with the screen refresh rate. When the maximum number of pixels which can be panned is reached, the horizontal panning register may be reset and the start address in the CRT controller changed to accomplish further panning.
A problem with the smooth panning accomplished by the horizontal panning register is found in that when the limits of the video memory are reached at the normal end of line data, the data panned into the image will be that of the next scan line giving a wrap around effect from one edge of the screen to the other. This effect can be avoided by programming the offset register in the CRT controller sub-section to set a logical screen width which is wider than the actual screen or providing space between scan lines in video memory. The offset register is bit oriented and increasing the value of the logical screen width provides extra memory bytes between each scan line.
Normally in such a system, the offset register is programmed in mode HEX 10 such that the next row is larger than the current row by 80. Incrementing of the display start address in the CRT controller sub section may be accomplished at the beginning of the vertical retrace of each screen so no flicker or jerky movement of the display will be seen. Although smooth pan may be accomplished, it is not possible to smooth pan in this video mode without refreshing the entire screen memory after every pan. Thus, such a system is somewhat ineffective in the smooth panning and display of any dynamic data and is unable to be used with real time data acquisition and display requirements. Some systems have been developed to accelerate the speed at which smooth panning may be accomplished, but these have been of relative high cost and complexity thereby inhibiting their general use.